Structures for and method of silicide formation on memory array and peripheral logic devices
US7517737B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2007 |
| Grant date | Apr 14, 2009 |
| Priority date | — |
| Expiry date | May 23, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/40
Abstract
A memory device and peripheral circuitry on a substrate are described, made by a process that includes forming a charge trapping structure having a first thickness over a first area. A first gate dielectric layer having a second thickness is formed for low-voltage transistors. A second gate dielectric layer having a third thickness, greater than the second thickness, is formed for high-voltage transistors. Polysilicon is deposited and patterned to define word lines and transistor gates. The thickness of the second gate dielectric layer in regions adjacent the gates, and over a source and drain regions, is reduced to a thickness that is close to that of the second thickness. Dopants are implanted for formation of source and drain regions in the second and third areas. A silicon nitride spacer material is deposited over the word lines and gates, and etched to form sidewall spacers on the gates. Dopants are implanted aligned with the sidewall spacers in the second and third areas. The gate dielectric layers are selectively etched to expose the substrate adjacent the sidewall spacers, and to expose word lines and gates without exposing the substrate in the bit line contract regions. A …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.