Methods for fabricating a stress enhanced semiconductor device having narrow pitch and wide pitch transistors

US7521380B2 · kind B2 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Andrew Waite · Beverly, US
• Scott Luning · San Francisco, US
• Frank (Bin) Yang · Mahwah, US

Key dates

• Filing date: Apr 23, 2007
• Grant date: Apr 21, 2009
• Expiry date: Aug 29, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/201

Abstract

A method is provided for fabricating a semiconductor device on a semiconductor substrate. A plurality of narrow gate pitch transistors (NPTs) and wide gate pitch transistors (WPTs) are formed on and in the semiconductor substrate. The NPTs are spaced apart by a first distance, and the WPTs are spaced apart by a second distance greater than the first distance. A first stress liner layer is deposited overlying the NPTs, the WPTs and the semiconductor layer, an etch stop layer is deposited overlying the first stress liner layer, and a second stress liner layer is deposited overlying the etch stop layer. A portion of the second stress liner layer which overlies the WPTs is covered, and an exposed portion of the second stress liner layer which overlies the NPTs is removed to expose an exposed portion of the etch stop layer. The exposed portion of the etch stop layer which overlies the NPTs is removed.