Memory device using multi-layer with a graded resistance change
US7521704B2 · kind B2 · utility
13Cited by
11References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2005 |
| Grant date | Apr 21, 2009 |
| Priority date | — |
| Expiry date | Nov 8, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device using a multi-layer with a graded resistance change is provided. The memory device includes: a lower electrode; a data storage layer being located on the lower electrode and having the graded resistance change; and an upper electrode being located on the data storage layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.