Orientation-optimized PFETS in CMOS devices employing dual stress liners

US7525162B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Haizhou Yin · Poughkeepsie, US
• Katherine L. Saenger · Ossining, US
• Chun-Yung Sung · Poughkeepsie, US
• Kai Xiu · White Plains, US

Key dates

• Filing date: Sep 6, 2007
• Grant date: Apr 28, 2009
• Expiry date: Oct 22, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0167

Abstract

A PFET is provided on a silicon layer having a (110) surface orientation and located in a substrate. A compressive stress liner disposed on the gate and source/drain regions of the PFET generates a primary longitudinal compressive strain along the direction of the PFET channel. A tensile stress liner disposed on at least one NFET located transversely adjacent to the PFET generates a primary longitudinal tensile strain along the direction of the NFET channel. A secondary stress field from the at least one NFET tensile liner generates a beneficial transverse tensile stress in the PFET channel. The net benefits of the primary compressive longitudinal strain and the secondary tensile transverse stress are maximized when the azimuthal angle between the direction of the PFET channel and an in-plane [1 1 0] crystallographic direction in the (110) silicon layer is from about 25° to about 55.