Structure and method for manufacturing device with ultra thin SOI at the tip of a V-shape channel
US7528027B1 · kind B1 · utility
5Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2008 |
| Grant date | May 5, 2009 |
| Priority date | — |
| Expiry date | Mar 25, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
An SOI CMOS structure includes a v-shape trench in a pFet region. The v-shape trench has a surface in a (111) plane and extends into an SOI layer in the pFet region. A layer, such as a gate oxide or high-k material, is formed in the v-shape trench. Poly-Si is deposited on top of the layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.