Method for improved fabrication of a semiconductor using a stress proximity technique process
US7531401B2 · kind B2 · utility
5Cited by
1References
18Claims
0Family size
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Key dates
| Filing date | Feb 8, 2007 |
| Grant date | May 12, 2009 |
| Priority date | — |
| Expiry date | Aug 10, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/938
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved method for applying stress proximity technique process on a semiconductor device and the improved device is disclosed. In one embodiment, the method utilizes an additional set of sidewall spacers on one or more NFET devices during the fabrication process. This protects the one or more of the NFET devices during the activation of a compressive PFET stress liner, thereby reducing the compressive forces on the one or more NFET devices, and creating a semiconductor device with improved performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.