Reduction of damage to thermal interface material due to asymmetrical load
US7544542B2 · kind B2 · utility
13Cited by
25References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 7, 2006 |
| Grant date | Jun 9, 2009 |
| Priority date | — |
| Expiry date | Aug 10, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various method and apparatus for packaging an integrated circuit are provided. In one aspect, a method of packaging an integrated circuit is provided that includes coupling an integrated circuit to a substrate, mixing an adhesive with a plurality of particles, and coupling a lid to the substrate with the adhesive. At least a portion of the plurality of particles in the adhesive oppose compressive force from the lid to restrict rotation of the lid relative to the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.