Semiconductor heterostructure
US7544976B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2007 |
| Grant date | Jun 9, 2009 |
| Priority date | — |
| Expiry date | Jul 21, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor heterostructure that includes a support substrate with a first in-plane lattice parameter, a buffer structure formed on the support substrate and having on top in a relaxed state a second in-plane lattice parameter, and a multi-layer stack of ungraded layers formed on the buffer structure. This semiconductor hetero-structure possess a lower surface roughness than other heterostructures. In the heterostructure, the ungraded layers are strained layers that comprise at least one strained smoothing layer of a semiconductor material having in a relaxed state a third in-plane lattice parameter which has a value between the first and the second lattice parameter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.