Methods of forming lead free solder bumps

US7547623B2 · kind B2 · utility

Assignee

• Unitive International · NL

Inventors

• J. Daniel Mis · Cary, US
• Gretchen Adema · Raleigh, US
• Susan Bumgarner · Clearwater, US
• Pooja Chilukuri · Morrisville, US
• Christine Rinne · Apex, US
• Glenn Rinne · Apex, US

Key dates

• Filing date: Jun 29, 2005
• Grant date: Jun 16, 2009
• Expiry date: Jun 15, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/19043
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Methods of forming an electronic device may include forming an under bump seed metallurgy layer on an electronic substrate. A nickel layer may be formed on the under bump seed metallurgy layer so that the under bump seed metallurgy layer is between the nickel layer and the electronic substrate, and portions of the under bump seed metallurgy layer may be free of the nickel layer. In addition, a solder layer may be formed on the nickel layer so that the nickel layer is between the solder layer and the under bump seed metallurgy layer. In addition, a copper layer may be formed on the under bump seed metallurgy layer before forming the nickel layer with portions of the under bump seed metallurgy layer being free of the copper layer. Accordingly, the under bump seed metallurgy layer may be between the copper layer and the electronic substrate, and the copper layer may be between the under bump seed metallurgy layer and the nickel layer. Related structures are also discussed.