J. Daniel Mis
11Patents
7h-index
13Co-inventors
63Inventor score
Filing activity: Jan 8, 1991 → Oct 19, 2010
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6762122B2 | Methods of forming metallurgy structures for wire and solder bonding | Electricity | 81 | Expired |
| US5171642A | Multilayered intermetallic connection for semiconductor devices | Emerging Cross-Sectional Technologies | 23 | Expired |
| US7427557B2 | Methods of forming bumps using barrier layers as etch masks | Electricity | 17 | Expired |
| US5470781A | Method to reduce stress from trench structure on SOI wafer | Electricity | 14 | Expired |
| US7358174B2 | Methods of forming solder bumps on exposed metal pads | Electricity | 14 | Expired |
| US7547623B2 | Methods of forming lead free solder bumps | Electricity | 7 | Active |
| US7839000B2 | Solder structures including barrier layers with nickel and/or copper | Electricity | 7 | Active |
| US7834454B2 | Electronic structures including barrier layers defining lips | Electricity | 5 | Active |
| US7994043B1 | Lead free alloy bump structure and fabrication method | Electricity | 4 | Active |
| US7665652B2 | Electronic devices including metallurgy structures for wire and solder bonding | Electricity | 3 | Active |
| US8487432B2 | Electronic structures including barrier layers and/or oxidation barriers defining lips and related methods | Electricity | 2 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.