Tuning programmable logic devices for low-power design implementation
US7549139B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2004 |
| Grant date | Jun 16, 2009 |
| Priority date | — |
| Expiry date | Nov 15, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356173
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of operating a programmable logic device includes the steps of using a full VDD supply voltage to operate a first set of active blocks of the programmable logic device, and using a reduced supply voltage (e.g., 0.9 VDD) to operate a second set of active blocks of the programmable logic device. A timing analysis is performed to determine the maximum available timing slack in each active block. Active blocks having a smaller timing slack are grouped in the first set, and are coupled to receive the full VDD supply voltage. Active blocks having a larger timing slack are grouped in the second set, and are coupled to receive the reduced VDD supply voltage. As a result, the active blocks in the second set exhibit reduced power consumption, without adversely affecting the overall speed of the programmable logic device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.