Method for reducing resist poisoning during patterning of silicon nitride layers in a semiconductor device

US7550396B2 · kind B2 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Kai Frohberg · Meißen, DE
• Volker Grimm · Neustadt an der Donau, DE
• Sven Mueller · Rockenberg, DE
• Matthias Lehr · Dresden, DE
• Ralf Richter · Dresden, DE
• Jochen Klais · Radebeul, DE
• Martin Mazur · Pulsnitz, DE
• Heike Salz · Radebeul, DE
• Joerg Hohage · Dresden, DE
• Matthias Schaller · Dresden, DE

Key dates

• Filing date: May 1, 2007
• Grant date: Jun 23, 2009
• Expiry date: Aug 6, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/601
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

By performing a plasma treatment for efficiently sealing the surface of a stressed dielectric layer containing silicon nitride, an enhanced performance during the patterning of contact openings may be achieved, since nitrogen-induced resist poisoning may be significantly reduced during the selective patterning of stressed layers of different types of intrinsic stress.