Implementation of column redundancy for a flash memory with a high write parallelism
US7551498B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2006 |
| Grant date | Jun 23, 2009 |
| Priority date | — |
| Expiry date | Dec 15, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/846
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A redundant memory array has r columns of redundant memory cells, r redundant senses, and a redundant column decoder. Redundant address registers store addresses of defective regular memory cells. Redundant latches are provided in n groups of r latches. Redundancy comparison logic compares addresses of defective regular memory cells with an external input address. If the comparison is true, what is provided is: a DISABLE_LOAD signal to disable the regular senses for one of the n groups of m columns, an ENABLE_LATCH signal to one of the n groups of m columns to disables corresponding regular senses, and one or r REDO signals to a respective one of the r redundant latches in one of the n groups that is disabled. The selected one of the redundant latches activates one of the r redundant senses to access a redundant column.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.