Field effect transistor comprising a stressed channel region and method of forming the same
US7556996B2 · kind B2 · utility
4Cited by
2References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2007 |
| Grant date | Jul 7, 2009 |
| Priority date | — |
| Expiry date | Aug 6, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a field effect transistor comprises providing a substrate comprising, at least on a surface thereof, a first semiconductor material. A recess is formed in the substrate. The recess is filled with a second semiconductor material. The second semiconductor material has a different lattice constant than the first semiconductor material. A gate electrode is formed over the recess filled with the second semiconductor material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.