Thermally enhanced power semiconductor package system
US7557432B2 · kind B2 · utility
4Cited by
14References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2006 |
| Grant date | Jul 7, 2009 |
| Priority date | — |
| Expiry date | Nov 25, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a thermally enhanced power semiconductor package system comprising providing a power semiconductor die, forming an upper lead frame on the power semiconductor die and forming a lower lead frame below the power semiconductor die, wherein the upper lead frame and the lower lead frame are provided in an offset configuration relative to each other to provide two heat dissipation paths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.