Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability
US7558136B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2007 |
| Grant date | Jul 7, 2009 |
| Priority date | — |
| Expiry date | Aug 14, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell having an asymmetric connection for evaluating dynamic stability provides a mechanism for raising the performance of memory arrays beyond present levels/yields. By operating the cell and observing changes in performance caused by the asymmetry, the dynamic stability of the SRAM cell can be studied over designs and operating environments. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each crosscoupled stage. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. A memory array with at least one test cell can be fabricated in a production or test wafer and internal nodes of the memory cell can be probed to provide further information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.