Reliable high voltage gate dielectric layers using a dual nitridation process
US7560792B2 · kind B2 · utility
4Cited by
7References
4Claims
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Key dates
| Filing date | Jan 24, 2007 |
| Grant date | Jul 14, 2009 |
| Priority date | — |
| Expiry date | Jan 24, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0144
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Dual gate dielectric layers are formed on a semiconductor substrate for MOS transistor fabrication. A first dielectric layer (30) is formed on a semiconductor substrate (10). A first plasma nitridation process is performed on said first dielectric layer. The first dielectric layer (30) is removed in regions of the substrate and a second dielectric layer (50) is formed in these regions. A second plasma nitridation process is performed on the first dielectric layer and the second dielectric layer. MOS transistors (160, 170) are then fabricated using the dielectric layers (30, 50).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.