Formation of transistor having a strained channel region including a performance enhancing material composition utilizing a mask pattern

US7569437B2 · kind B2 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Frank Wirbeleit · Dresden, DE
• Andy Wei · Queensbury, US
• Roman Boschke · Dresden, DE

Key dates

• Filing date: Mar 21, 2007
• Grant date: Aug 4, 2009
• Expiry date: Jul 3, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/021
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

By forming a semiconductor alloy in a silicon-based active semiconductor region prior to the gate patterning, material characteristics of the semiconductor alloy itself may also be exploited in addition to the strain-inducing effect thereof. Consequently, device performance of advanced field effect transistors may be even further enhanced compared to conventional approaches using a strained semiconductor alloy in the drain and source regions.