Recessed gate for a CMOS image sensor

US7572701B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• James W. Adkisson · Jericho, US
• John J. Ellis-Monaghan · Grand Isle, US
• Mark D. Jaffe · Shelburne, US
• Jerome B. Lasky · South Burlington, US

Key dates

• Filing date: Apr 13, 2007
• Grant date: Aug 11, 2009
• Expiry date: Sep 9, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10F39/80

Abstract

A novel CMOS image sensor cell structure and method of manufacture. The imaging sensor comprises a substrate having an upper surface, a gate comprising a dielectric layer formed on the substrate and a gate conductor formed on the gate dielectric layer, a collection well layer of a first conductivity type formed below a surface of the substrate adjacent a first side of the gate conductor, a pinning layer of a second conductivity type formed atop the collection well at the substrate surface, and a diffusion region of a first conductivity type formed adjacent a second side of the gate conductor, the gate conductor forming a channel region between the collection well layer and the diffusion region. A portion of the bottom of the gate conductor is recessed below the surface of the substrate. Preferably, a portion of the gate conductor is recessed at or below a bottom surface of the pinning layer to a depth such that the collection well intersects the channel region thereby eliminating any potential barrier interference caused by the pinning layer.