Inverse slope isolation and dual surface orientation integration

US7575968B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Mariam Sadaka · Austin, US
• Debby Eades · Manor, US
• Joe Mogab · Austin, US
• Bich-Yen Nguyen · Austin, US
• Melissa O. Zavala · Pflugerville, US
• Gregory S. Spencer · Pflugerville, US

Key dates

• Filing date: Apr 30, 2007
• Grant date: Aug 18, 2009
• Expiry date: May 1, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0167

Abstract

A semiconductor process and apparatus provide a high performance CMOS devices (108, 109) with hybrid or dual substrates by etching a deposited oxide layer (62) using inverse slope isolation techniques to form tapered isolation regions (76) and expose underlying semiconductor layers (41, 42) in a bulk wafer structure prior to epitaxially growing the first and second substrates (84, 82) having different surface orientations that may be planarized with a single CMP process. By forming first gate electrodes (104) over a first substrate (84) that is formed by epitaxially growing (100) silicon and forming second gate electrodes (103) over a second substrate (82) that is formed by epitaxially growing (110) silicon, a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes having improved hole mobility.