Patent · US Active

Different embedded strain layers in PMOS and NMOS transistors and a method of forming the same

US7579262B2 · kind B2 · utility

16Cited by

8References

23Claims

0Family size

Assignee

Advanced Micro Devices, Inc. · US

Inventors

Jan Hoentschel · Dresden, DE
Andy Wei · Queensbury, US
Manfred Horstmann · Dresden, DE
Thorsten Kammler · Radeberg, DE

Key dates

Filing date	Nov 21, 2006
Grant date	Aug 25, 2009
Priority date	—
Expiry date	Apr 11, 2028

Classification

Technology area (CPC H)Electricity
CPC primaryH10D64/668
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

By omitting a growth mask or by omitting lithographical patterning processes for forming growth masks, a significant reduction in process complexity may be obtained for the formation of different strained semiconductor materials in different transistor types. Moreover, the formation of individually positioned semiconductor materials in different transistors may be accomplished on the basis of a differential disposable spacer approach, thereby combining high efficiency with low process complexity even for highly advanced SOI transistor devices.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.