Method and mechanism for controlling power consumption of an integrated circuit
US7581124B1 · kind B1 · utility
34Cited by
50References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2006 |
| Grant date | Aug 25, 2009 |
| Priority date | — |
| Expiry date | Mar 4, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A PLD includes a plurality of logic blocks, a test circuit, and a test pin set. The logic blocks are coupled to gating circuits that selectively adjust an operating voltage for the blocks in response to control signals. During operation of the PLD, the control signals are updated in response to externally-generated signals provided to the PLD via the test pin set and routed to the logic blocks using the test circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.