Methods of fabricating non-volatile memory with integrated peripheral circuitry and pre-isolation memory cell formation
US7582529B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2008 |
| Grant date | Sep 1, 2009 |
| Priority date | — |
| Expiry date | Apr 2, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
Non-volatile semiconductor memory devices with dual control gate memory cells and methods of forming the same using integrated peripheral circuitry formation are provided. Strips of charge storage material elongated in a row direction across the surface of a substrate with strips of tunnel dielectric material therebetween are formed. Forming the strips defines the dimension of the resulting charge storage structures in the column direction. The strips of charge storage material can include multiple layers of charge storage material to form composite charge storage structures in one embodiment. Strips of control gate material are formed between strips of charge storage material adjacent in the column direction. The strips of charge storage and control gate material are divided along their lengths in the row direction as part of forming isolation trenches and columns of active areas. After dividing the strips, the charge storage material at the peripheral circuitry region of the substrate is etched to define a gate dimension in the column direction for a peripheral transistor. Control gate interconnects can be formed to connect together rows of isolated control gates to extrinsically…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.