Method for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop

US7585705B2 · kind B2 · utility

Assignee

• Alpha and Omega Semiconductor, Ltd. · US

Inventors

• Mengyu Pan · Shanghai, CN
• Zengyi He · Shanghai, CN
• Kaiyu Chen · San Jose, US

Key dates

• Filing date: Nov 29, 2007
• Grant date: Sep 8, 2009
• Expiry date: Feb 18, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D88/01

Abstract

A method and device structure are disclosed for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop the trench MOSFET. The ESD protection module has a low temperature oxide (LTO) bottom layer whose patterning process is found to cause the gate oxide damage. The method includes: a) Fabricate numerous trench MOSFETs on a wafer. b) Add a Si3N4 isolation layer, capable of preventing the LTO patterning process from damaging the gate oxide, atop the wafer. c) Add numerous ESD protection modules atop the Si3N4 isolation layer. d) Remove those portions of the Si3N4 isolation layer that are not beneath the ESD protection modules. In one embodiment, hydrofluoric acid is used as a first etchant for patterning the LTO while hot phosphoric acid is used as a second etchant for removing portions of the Si3N4 isolation layer.