Logic block control architectures for programmable logic devices

US7592834B1 · kind B1 · utility

Assignee

• Lattice Semiconductor Corporation · US

Inventors

• Om P. Agrawal · Los Altos, US
• Xiaojie He · Austin, US
• Sajitha Wijesuriya · Macungie, US
• Barry Britton · Orefield, US
• Ming H. Ding · San Jose, US
• Jun Zhao · Mianyang, CN

Key dates

• Filing date: Jun 30, 2008
• Grant date: Sep 22, 2009
• Expiry date: Jun 30, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K19/17728
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

In one embodiment of the invention, a programmable logic device comprises configuration memory adapted to store configuration data and a plurality of programmable logic blocks. At least one programmable logic block includes a plurality of dual-slice logic blocks, each dual-slice logic block including first and second slices, each slice including at least two lookup tables (LUTs) and a register. The programmable logic block further includes control logic adapted for selecting control signals separately at a programmable block level, a dual-slice block level, and a register level, the control logic responsive to configuration data stored within the configuration memory.