Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devices

US7598545B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Eduard A. Cartier · New York, US
• Matthew W. Copel · Yorktown Heights, US
• Bruce B. Doris · Brewster, US
• Rajarao Jammy · Hopewell Junction, US
• Young-Hee Kim · Potsdam, US
• Barry P. Linder · Hastings-on-Hudson, US
• Vijay Narayanan · New York, US
• Vamsi K. Paruchuri · New York, US
• Keith Kwong Hon Wong · Wappingers Falls, US

Key dates

• Filing date: Apr 21, 2005
• Grant date: Oct 6, 2009
• Expiry date: Sep 6, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0177

Abstract

The present invention is directed to CMOS structures that include at least one nMOS device located on one region of a semiconductor substrate; and at least one pMOS device located on another region of the semiconductor substrate. In accordance with the present invention, the at least one nMOS device includes a gate stack comprising a gate dielectric, a low workfunction elemental metal having a workfunction of less than 4.2 eV, an in-situ metallic capping layer, and a polysilicon encapsulation layer and the at least one pMOS includes a gate stack comprising a gate dielectric, a high workfunction elemental metal having a workfunction of greater than 4.9 eV, a metallic capping layer, and a polysilicon encapsulation layer. The present invention also provides methods of fabricating such a CMOS structure.