Silicided polysilicon spacer for enhanced contact area
US7598572B2 · kind B2 · utility
3Cited by
5References
2Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Oct 25, 2006 |
| Grant date | Oct 6, 2009 |
| Priority date | — |
| Expiry date | Jul 14, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device having an increased source/drain contact area by a formed silicided polysilicon spacer. The polysilicon sidewall spacer is formed having a height less than seventy percent of said gate conductor height, and having a continuous surface silicide layer over the deep source and drain regions. The contact area is enhanced by the silicided polysilicon spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.