Method for forming solder joints for a flip chip assembly
US7601612B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2005 |
| Grant date | Oct 13, 2009 |
| Priority date | — |
| Expiry date | Dec 7, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method for forming a solder joint for a package arrangement with a dispersed Sn microstructure provides a flip chip on a package, with a flip chip having solder bumps to be connected by eutectic solder joints to pads on the package. The eutectic solder is reflowed at a solder bump/pad interface with a eutectic reflow profile that is configured to achieve eutectic solder joints having substantially evenly distributed Sn grains. The eutectic reflow profile includes an increased cooling rate and decreased hold time with a higher peak temperature. A defined ratio of the pad openings in the solder mask to the under bump metallurgy is provided. The eutectic reflow profile and the defined ratio prolong fatigue life in the package arrangement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.