Method for manufacturing silicon wafers
US7601644B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 2005 |
| Grant date | Oct 13, 2009 |
| Priority date | — |
| Expiry date | Mar 18, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/30604
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This silicon wafer production process comprises in the order indicated a planarization step, in which the front surface and the rear surface of a wafer are ground or lapped, a single-wafer acid etching step, in which an acid etching liquid is supplied to the surface of the wafer while spinning and the entire wafer surface is etched to control the surface roughness Ra to 0.20 μm or less, and a double-sided simultaneous polishing step, in which the front surface and the rear surface of the acid etched wafer are polished simultaneously. The process may comprise a single-sided polishing step, in which the top and bottom of the acid etched wafer are polished in turn, instead of the double-sided simultaneously polishing step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.