Area efficient routing architectures for programmable logic devices

US7605606B1 · kind B1 · utility

Assignee

• Lattice Semiconductor Corporation · US

Inventors

• Ming H. Ding · San Jose, US
• Sajitha Wijesuriya · Macungie, US
• Jun Zhao · Mianyang, CN
• Om P. Agrawal · Los Altos, US
• Barry Britton · Orefield, US
• Xiaojie He · Austin, US

Key dates

• Filing date: Aug 3, 2006
• Grant date: Oct 20, 2009
• Expiry date: Oct 20, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K19/17736
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

Systems and methods provide programmable logic block architectures and routing architectures for the programmable logic blocks. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks and a plurality of logic block slices within each of the programmable logic blocks. A first routing circuit provides global signal routing within the programmable logic device for the corresponding programmable logic block. A first input routing circuit receives signals from the first routing circuit and routes the signals to the logic block slices within the corresponding programmable logic block.