Method for non-volatile memory with reduced erase/write cycling during trimming of initial programming voltage
US7606091B2 · kind B2 · utility
10Cited by
35References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2006 |
| Grant date | Oct 20, 2009 |
| Priority date | — |
| Expiry date | Sep 12, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
High performance non-volatile memory devices have the programming voltages trimmed for individual types of memory pages and word lines. A group of word lines within each erasable block of memory are tested in successive program loops to minimize the problem of incurring excessive number of erase/program cycles. An optimum programming voltage for a given type of memory pages is derived from statistical results of a sample of similar of memory pages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.