Strained layers within semiconductor buffer structures
US7608526B2 · kind B2 · utility
15Cited by
13References
39Claims
0Family size
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Key dates
| Filing date | Jul 24, 2006 |
| Grant date | Oct 27, 2009 |
| Priority date | — |
| Expiry date | Dec 10, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02532
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor workpiece including a substrate, a relaxed buffer layer including a graded portion formed on the substrate, and at least one strained transitional layer within the graded portion of the relaxed buffer layer and method of manufacturing the same. The at least one strained transitional layer reduces an amount of workpiece bow due to differential coefficient of thermal expansion (CTE) contraction of the relaxed buffer layer relative to CTE contraction of the substrate
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.