Method and implementation of stress test for MRAM
US7609543B2 · kind B2 · utility
2Cited by
6References
29Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 27, 2007 |
| Grant date | Oct 27, 2009 |
| Priority date | — |
| Expiry date | Dec 1, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/12005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Voltage and current stress for magnetic random access memory (MRAM) cells can weed out potential early failure cells. Method and circuit implementation of such a stress test for a MRAM comprise coupling a stress test circuit to the read bus of the MRAM and stressing the Magnetic Tunnel Junctions (MTJS) by tying them to ground by activating isolation transistors associated with them. Read word lines control which MTJs are stressed Both the method and implementation can be used for any memory cells based on resistance differences, such as Phase RAM or Spin Valve MRAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.