Mechanism for hardware tracking of return address after tail call elimination of return-type instruction
US7610474B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2006 |
| Grant date | Oct 27, 2009 |
| Priority date | — |
| Expiry date | Feb 12, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique maintains return address stack (RAS) content and alignment of a RAS top-of-stack (TOS) pointer upon detection of a tail-call elimination of a return-type instruction. In at least one embodiment of the invention, an apparatus includes a processor pipeline and at least a first return address stack for maintaining a stack of return addresses associated with instruction flow at a first stage of the processor pipeline. The processor pipeline is configured to maintain the first return address stack unchanged in response to detection of a tail-call elimination sequence of one or more instructions associated with a first call-type instruction encountered by the first stage. The processor pipeline is configured to push a return address associated with the first call-type instruction onto the first return address stack otherwise.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.