Patent · US Active

Dual damascene patterning method

US7611986B2 · kind B2 · utility

2Cited by

5References

25Claims

0Family size

Assignee

IMEC · BE

Inventors

Jan Van Olmen · Leuven, BE
Marleen Van Hove · Blanden, BE
Herbert Struyf · Kontich, BE
Dirk Hendrickx · Grez-Doiceau, BE
Serge Vanhaelemeersch · Leuven, BE
Werner Boullart · Leuven, BE

Key dates

Filing date	Apr 10, 2006
Grant date	Nov 3, 2009
Priority date	—
Expiry date	Apr 29, 2027

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/0002
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method for patterning a dual damascene structure in a semiconductor substrate is disclosed. The patterning is a metal hardmask based pattering eliminating at least resist poisoning and further avoiding or at least minimizing low-k damage. The method can be used as a full-via-first patterning method or a partial-via-first patterning method.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.