Integrated circuit manufacturing method using hard mask

US7615484B2 · kind B2 · utility

Assignees

• Chartered Semiconductor Manufacturing LTD · SG
• Infineon Technologies North America Corp. · US
• International Business Machines Corporation · US

Inventors

• Wuping Liu · Singapore, SG
• Michael Beck · Milpitas, US
• John A. Fitzsimmons · Poughkeepsie, US

Key dates

• Filing date: Apr 24, 2007
• Grant date: Nov 10, 2009
• Expiry date: Jul 4, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76835
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An integrated circuit hard mask processing system is provided including providing a substrate having an integrated circuit; forming an interconnect layer over the integrated circuit; applying a low-K dielectric layer over the interconnect layer; applying a hard mask layer over the low-K dielectric layer; forming a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer; applying a first fluid and a second fluid in the via opening for removing an overhang of the hard mask layer; depositing an interconnect metal in the via opening; and chemical-mechanical polishing the interconnect metal and the ultra low-K dielectric layer.