IC chip at-functional-speed testing with process coverage evaluation
US7620921B2 · kind B2 · utility
23Cited by
16References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2007 |
| Grant date | Nov 17, 2009 |
| Priority date | — |
| Expiry date | Oct 4, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems and program products for evaluating an IC chip are disclosed. In one embodiment, the method includes running a statistical static timing analysis (SSTA) of a full IC chip design; creating at-functional-speed test (AFST) robust paths for an IC chip, the created robust paths representing a non-comprehensive list of AFST robust paths for the IC chip; and re-running the SSTA with the SSTA delay model setup based on the created robust paths. A process coverage is calculated for evaluation from the SSTA runnings; and a particular IC chip is evaluated based on the process coverage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.