Methods for fabricating dual material gate in a semiconductor device
US7635648B2 · kind B2 · utility
2Cited by
10References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2008 |
| Grant date | Dec 22, 2009 |
| Priority date | — |
| Expiry date | Apr 10, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating dual material gate structures in a device is provided. The dual material gate structures have different gate electrode materials in different regions of the device. In one embodiment, the method includes providing a substrate having a patterned first gate electrode and a patterned first gate dielectric layer disposed on the substrate, removing a portion of the first gate electrode from the substrate to define a trench on the substrate, and filling the trench to form a second gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.