Method and structure for coordinating instruction execution in out-of-order processor execution using an instruction including an artificial register dependency
US7650487B2 · kind B2 · utility
2Cited by
3References
25Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 8, 2006 |
| Grant date | Jan 19, 2010 |
| Priority date | — |
| Expiry date | Mar 8, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3854
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for coordinating execution of instructions in a processor that allows instructions to execute out-of-order includes decoding a particular instruction that is defined in accordance with an instruction set of the processor. A helper sequence of instructions that corresponds to the particular instruction is then introduced into a stream of executable operations. The corresponding helper sequence includes a first artificial dependency instruction that codes a dependency on a register that is not actually employed as a register source or target for an operation performed by the particular instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.