Integrated circuit package system including stacked die
US7652376B2 · kind B2 · utility
5Cited by
206References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2008 |
| Grant date | Jan 26, 2010 |
| Priority date | — |
| Expiry date | Sep 22, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit package system is provided including providing a wafer with bond pads formed on the wafer. A solder bump is deposited on one or more bond pads. The bond pads and the solder bump are embedded within a mold compound formed on the wafer. A groove is formed in the mold compound to expose a portion of the solder bump. The wafer is singulated into individual die structures at the groove.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.