Retention margin program verification
US7652918B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2006 |
| Grant date | Jan 26, 2010 |
| Priority date | — |
| Expiry date | Dec 28, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system, comprising an array of storage elements divided into logical blocks and pages within said logical blocks and a managing circuit is provided. The managing circuit is in communication with said array of storage elements and performs programming and reading operations. The programming operations include programming a plurality of multi-state storage data. The reading operations include defining an retention margin between adjacent data thresholds, determining whether bits are present in a portion of the data retention margin, and if the number of bits in the portion of retention margin exceeds a threshold, generating an error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.