Patent · US Active

Test algorithm selection in memory built-in self test controller

US7653845B2 · kind B2 · utility

10Cited by

9References

15Claims

0Family size

Assignee

Advanced Micro Devices, Inc. · US

Inventors

Siegfried Kay Hesse · Dresden, DE
Markus Seuring · Stuttgart, DE
Thomas Herrmann · Federal Way, US

Key dates

Filing date	Jul 11, 2006
Grant date	Jan 26, 2010
Priority date	—
Expiry date	Sep 1, 2027

Classification

Technology area (CPC G)Physics
CPC primaryG11C29/16
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An integrated circuit chip is provided that comprises on-chip memory and test circuitry. The test circuitry is configured to perform operational testing of the on-chip memory. The test circuitry comprises a controller which is configured to perform a selection out of a plurality of test algorithms to perform the operational testing. The plurality of test algorithms includes a fault detection test algorithm to perform operational testing of the on-chip memory in order to detect whether or not there is a memory fault, without locating the memory fault. The plurality of test algorithms further includes a fault location test algorithm to perform operational testing of the on-chip memory in order to detect and locate a memory fault. Further, a method to perform a memory built-in self test and an MBIST (Memory Built-In Self Test) control circuit template are provided.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.