Field effect transistors (FETS) with inverted source/drain metallic contacts, and method of fabrication same
US7659160B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2007 |
| Grant date | Feb 9, 2010 |
| Priority date | — |
| Expiry date | Oct 24, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to an field effect transistor (FET) comprising an inverted source/drain metallic contact that has a lower portion located in a first, lower dielectric layer and an upper portion located in a second, upper dielectric layer. The lower portion of the inverted source/drain metallic contact has a larger cross-sectional area than the upper portion. Preferably, the lower portion of the inverted source/drain metallic contact has a cross-sectional area ranging from about 0.03 μm2 to about 3.15 μm2, and such an inverted source/drain metallic contact is spaced apart from a gate electrode of the FET by a distance ranging from about 0.001 μm to about 5 μm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.