Transistor having an embedded tensile strain layer with reduced offset to the gate electrode and a method for forming the same

US7659213B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Andy Wei · Queensbury, US
• Thorsten Kammler · Radeberg, DE
• Jan Hoentschel · Dresden, DE
• Manfred Horstmann · Dresden, DE

Key dates

• Filing date: Dec 5, 2006
• Grant date: Feb 9, 2010
• Expiry date: Apr 1, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0227
• WIPO field: Surface technology, coating
• WIPO sector: Chemistry

Abstract

By incorporating carbon by means of ion implantation and a subsequent flash-based or laser-based anneal process, strained silicon/carbon material with tensile strain may be positioned in close proximity to the channel region, thereby enhancing the strain-inducing mechanism. The carbon implantation may be preceded by a pre-amorphization implantation, for instance on the basis of silicon. Moreover, by removing a spacer structure used for forming deep drain and source regions, the degree of lateral offset of the strained silicon/carbon material with respect to the gate electrode may be determined substantially independently from other process requirements. Moreover, an additional sidewall spacer used for forming metal silicide regions may be provided with reduced permittivity, thereby additionally contributing to an overall performance enhancement.