CMOS device and method of manufacturing same

US7663192B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Bernhard Sell · Dresden, DE
• Anand S. Murthy · Beaverton, US
• Mark Liu · West Linn, US
• Daniel B. Aubertine · North Plains, US

Key dates

• Filing date: Jun 30, 2008
• Grant date: Feb 16, 2010
• Expiry date: Jul 30, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0174

Abstract

A CMOS device includes NMOS (110) and PMOS (130) transistors, each of which include a gate electrode (111, 131) and a gate insulator (112, 132) that defines a gate insulator plane (150, 170). The transistors each further include source/drain regions (113/114, 133/134) having a first portion (115, 135) below the gate insulator plane and a second portion (116, 136) above the gate insulator plane, and an electrically insulating material (117). The NMOS transistor further includes a blocking layer (121) having a portion (122) between the gate electrode and a source contact (118) and a portion (123) between the gate electrode and a drain contact (119). The PMOS transistor further includes a blocking layer (141) having a portion (142) between the source region and the insulating material and a portion (143) between the drain region and the insulating material.