Double trench for isolation of semiconductor devices
US7667270B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2006 |
| Grant date | Feb 23, 2010 |
| Priority date | — |
| Expiry date | Jun 24, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76229
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device has a substrate (50), a buried layer (55), an active area extending from a surface contact to the buried layer, an insulator (130) in a first trench extending towards the buried layer, to isolate the active area, and a second insulator (130) in a second deep trench and extending through the buried layer to isolate the buried layer and the active area from other parts of the substrate. This double trench can help reduce the area needed for the electrical isolation between the active device and the other devices. Such reduction in area can enable greater integration or more cells in a multi cell super-MOS device, and so improve performance parameters such as Ron. The double trench can be manufactured using a first mask to etch both trenches at the same time, and subsequently using a second mask to etch the second deep trench deeper.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.