Semiconductor device, testing and manufacturing methods thereof
US7668027B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2006 |
| Grant date | Feb 23, 2010 |
| Priority date | — |
| Expiry date | Mar 2, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/50012
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In order to easily perform a timing test on a memory interface included in a semiconductor device so as to satisfy a restriction on latency, the present invention provides a semiconductor device with the memory interface including: a clock output terminal that outputs a clock signal associated with an operation of a memory connected to the memory interface; a command terminal that outputs a command signal associated with control of a state of the memory; a data terminal that exchanges a data signal with the memory; and a data strobe terminal that exchanges a data strobe signal for establishing the data signal. This semiconductor device includes a testing terminal that outputs in advance a signal for starting a test on the memory interface apart from the command signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.