Electronic packages
US7671436B2 · kind B2 · utility
2Cited by
1References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 2, 2008 |
| Grant date | Mar 2, 2010 |
| Priority date | — |
| Expiry date | Sep 9, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10674
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Assemblies involving integrated circuit dies (e.g. packaged integrated circuits) and packaged dies electrically connected to circuit boards at times mechanically fail at conducting pads used for electrical interconnection. Such failure is mitigated by underlying appropriate pads with a compliant region having specific characteristics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.