Computer system having daisy chained memory chips
US7673093B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2006 |
| Grant date | Mar 2, 2010 |
| Priority date | — |
| Expiry date | Mar 2, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4256
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system having a memory system having a memory controller and a memory. The memory controller is coupled to a processor and to the memory. The memory comprises one or more daisy chains of memory chips. An address/command word is chained through a daisy chain of memory chips and is handled by one of the memory chips in the daisy chain of memory chips. Data to be written to a memory chip is sent as part of the address/command word, or is transferred on an outgoing data bus chain. Data read from a memory chip is transferred on an incoming data bus chain. A daisy chain of memory chips can include memory chips on multiple carriers, or the daisy chain of memory chips can all be attached to a single carrier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.