Method and apparatus for compensating an integrated circuit layout for mechanical stress effects

US7673270B1 · kind B1 · utility

Assignee

• XILINX, INC. · US

Inventors

• Yan Wang · San Jose, US
• Nui Chong · San Jose, US
• Hong-Tsz Pan · Cupertino, US
• Bang-Thu Nguyen · Santa Clara, US
• Jonathan Ho · Fremont, US
• Qi Lin · Nanhu, CN
• Yuhao Luo · San Jose, US
• Hing Yee Angela Wong · San Jose, US
• Xin Wu · Fremont, US
• Yuezhen Fan · San Jose, US

Key dates

• Filing date: Mar 13, 2007
• Grant date: Mar 2, 2010
• Expiry date: Nov 12, 2027

Classification

• Technology area (CPC G): Physics
• CPC primary: G03F1/36
• WIPO field: Optics
• WIPO sector: Instruments

Abstract

Method and apparatus for compensating an integrated circuit design for mechanical stress effects. One aspect of the invention relates to designing an integrated circuit. Layout data is obtained that describes layers of the integrated circuit. At least one of the layers is analyzed to detect at least one structure susceptible to damage from mechanical stress. A bias is automatically added to each of the at least one structure to reduce mechanical stress of the at least one structure as fabricated. Augmented layout data is then provided for the integrated circuit.